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Ultra-low voltage and low-power voltage-mode DTMOS-based four-quadrant analog multiplierBabacan, YunusDTMOSFour-quadrant analog multiplierLow powerLow voltageHardwareSignal processingDynamic threshold mos (DTMOS)Four-quadrant analog multipliersLow voltagesMultiplier circuitsPost layout simulationTotal power consumptionComputer softwareThis paper presents a new four-quadrant analog multiplier based on a dynamic threshold MOS (DTMOS). The attractive features of this DTMOS transistor-based multiplier are its supply voltages and total power consumption, which were determined as ± 0.2 V and 18.4 nW, respectively. In addition, the study found no influences of the bulk effect of the transistors used in the proposed multiplier circuit. The layout of the four-quadrant analog multiplier occupied an active area of 44.6 µm × 21.93 µm and was drawn using Cadence Environment software, while the post-layout simulation results were performed using Cadence Environment with 0.18 µm TSMC CMOS technology parameters. All theoretical results and post-layout simulations confirmed the performance of the proposed circuit. © 2018, Springer Science+Business Media, LLC, part of Springer Nature.Springer New York LLC2019Articlehttps://rdlopen.rawdatalibrary.net/r/ebyu/13957https://doi.org/10.1007/s10470-018-1322-20925-1030enAnalog Integrated Circuits and Signal Processinginfo:eu-repo/semantics/openAccessinfo:eu-repo/semantics/articlehttps://ebyu-rdlopen.rawdatalibrary.net/tr/items/ebyu/13957