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Temperature dependent current-voltage characteristics of the Zn/ZnO/n-Si/Au-Sb structure with ZnO interface layer grown on n-Si substrate by SILAR methodAli Yildirim, M.Güzeldir, B.Ate, A.Salam, M.Barrier inhomogeneityInterface layerSandwich structureSILARZnOAdsorptionDistillationElectric resistanceInterfaces (materials)Ohmic contactsSandwich structuresScanning electron microscopySiliconX ray diffractionZinc oxideAbnormal behaviorBarrier heightsBarrier inhomogeneitiesCurrent voltage curveExperimental valuesForward biasIdeality factorsIV characteristicsPolycrystalline structureRectifying behaviorsRoom temperatureSample temperatureSeries resistancesSi substratesSILAR methodThis is the first time; it was employed Successive Ionic Layer Adsorption and Reaction (SILAR) method in order to prepare Zn/ZnO/n-Si/Au-Sb sandwich structure. The ZnO interface layer was directly formed on n-type Si substrate using SILAR method. The X-ray diffraction (XRD) and scanning electron microscopy (SEM) studies were showed that the film is covered well on n-type Si substrate and have polycrystalline structure. An Au-Sb electrode was used as an ohmic contact. The Zn/ZnO/n-Si/Au-Sb sandwich structure demonstrated clearly rectifying behavior by the current-voltage (I-V) curves studied at room temperature. The sample temperature effect on the current-voltage (I-V) characteristics of Zn/ZnO/n-Si/Au-Sb structure was investigated in temperature range 80-320 K by steps of 20 K. The parameters such as barrier height, ideality factor and series resistance of this structure were calculated from the forward bias I-V characteristics as a function of sample temperature. It was seen that the ideality factor and series resistance were decreased; the barrier height were increased with increasing temperature. The experimental values of barrier height and ideality factor for this device were calculated as 0.808 eV and 1.519 at 320 K; 0.220 eV and 4.961 at 80 K, respectively. These abnormal behaviors can be explained by the barrier inhomogeneities at the metal-semiconductor (M-S) interface. © 2011 Elsevier B.V. All rights reserved.ELSEVIER SCIENCE BV2011Articlehttps://rdlopen.rawdatalibrary.net/r/ebyu/15741https://doi.org/10.1016/j.mee.2011.05.0250167-9317enMicroelectronic Engineeringinfo:eu-repo/semantics/openAccessinfo:eu-repo/semantics/articlehttps://ebyu-rdlopen.rawdatalibrary.net/tr/items/ebyu/15741