<?xml version="1.0" encoding="UTF-8"?><OAI-PMH xmlns="http://www.openarchives.org/OAI/2.0/" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://www.openarchives.org/OAI/2.0/ http://www.openarchives.org/OAI/2.0/OAI-PMH.xsd"><responseDate>2026-10-19T00:02:15Z</responseDate><request verb="GetRecord" identifier="oai:ebyu-rdlopen.rawdatalibrary.net:ebyu/16424" metadataPrefix="oai_dc">https://ebyu-rdlopen.rawdatalibrary.net/oai/request</request><GetRecord><record><header><identifier>oai:ebyu-rdlopen.rawdatalibrary.net:ebyu/16424</identifier><datestamp>2026-10-18T20:34:04Z</datestamp><setSpec>openaire</setSpec><setSpec>driver</setSpec><setSpec>com_ebyu_10000</setSpec><setSpec>col_ebyu_10001</setSpec></header><metadata><oai_dc:dc xmlns:oai_dc="http://www.openarchives.org/OAI/2.0/oai_dc/" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://www.openarchives.org/OAI/2.0/oai_dc/ http://www.openarchives.org/OAI/2.0/oai_dc.xsd"><dc:title>The Implementation of Logic Gates Using Only Memristor Based Neuristor</dc:title><dc:creator>Orman, Kamil</dc:creator><dc:creator>Babacan, Yunus</dc:creator><dc:subject>AND gate</dc:subject><dc:subject>OR gate</dc:subject><dc:subject>Neuron</dc:subject><dc:subject>Memristor</dc:subject><dc:subject>Neuristor</dc:subject><dc:subject>EMULATOR</dc:subject><dc:subject>SPIKING</dc:subject><dc:subject>MODEL</dc:subject><dc:subject>Engineering, Electrical &amp; Electronic</dc:subject><dc:subject>Materials Science, Multidisciplinary</dc:subject><dc:subject>Engineering</dc:subject><dc:subject>Materials Science</dc:subject><dc:description>One can learn about memristor-based neuron circuits in literature if one wishes to implement more effective circuits, as they are linear, have a high density, and consume little energy. This paper presents two logic gates based on memristor-based neurons. The neuron circuit can float, and therefore can be used as a circuit element. Electronic neurons, or neuristors, generate spikes when DC current is applied to them; likewise, the proposed logic gates generate spikes when appropriate inputs are applied to them. We simulated the proposed gates with SPICE using TSMC 0.18 mu m CMOS process models.</dc:description><dc:publisher>SOC MICROELECTRONICS, ELECTRON COMPONENTS MATERIALS-MIDEM</dc:publisher><dc:date>2021</dc:date><dc:type>Article</dc:type><dc:identifier>https://rdlopen.rawdatalibrary.net/r/ebyu/16424</dc:identifier><dc:identifier>https://doi.org/10.33180/infmidem2021.203</dc:identifier><dc:identifier>0352-9045</dc:identifier><dc:language>en</dc:language><dc:relation>INFORMACIJE MIDEM-JOURNAL OF MICROELECTRONICS ELECTRONIC COMPONENTS AND MATERIALS</dc:relation><dc:rights>info:eu-repo/semantics/openAccess</dc:rights><dc:type>info:eu-repo/semantics/article</dc:type><dc:identifier>https://ebyu-rdlopen.rawdatalibrary.net/tr/items/ebyu/16424</dc:identifier></oai_dc:dc></metadata></record></GetRecord></OAI-PMH>