Gul, Fatih; Babacan, Yunus

A semiconductor memristor device based on a 300-nm ZnO thin film was fabricated by direct-current reactive sputter. The memristive behavior of this device was confirmed by time dependent current–voltage (I-V-t) measurements, and the distinctive pinched hysteresis I-V loops of the memristor were observed. Structural analysis of the ZnO memristor was carried out using both X-ray powder diffraction (XRD) and scanning electron microscopy (SEM). After physical implementation of the memristor, an operational transconductance amplifier (OTA) based memristor circuit was designed to emulate the ZnO-based semiconductor memristor for use in memristor-based circuit applications. All simulations were in good agreement with experimental results. In addition, a comparison of the proposed circuit with other memristor emulators was presented.

Ali Yildirim, M.; Güzeldir, B.; Ate, A.; Salam, M.

This is the first time; it was employed Successive Ionic Layer Adsorption and Reaction (SILAR) method in order to prepare Zn/ZnO/n-Si/Au-Sb sandwich structure. The ZnO interface layer was directly formed on n-type Si substrate using SILAR method. The X-ray diffraction (XRD) and scanning electron microscopy (SEM) studies were showed that the film is covered well on n-type Si substrate and have polycrystalline structure. An Au-Sb electrode was used as an ohmic contact. The Zn/ZnO/n-Si/Au-Sb sandwich structure demonstrated clearly rectifying behavior by the current-voltage (I-V) curves studied at room temperature. The sample temperature effect on the current-voltage (I-V) characteristics of Zn/ZnO/n-Si/Au-Sb structure was investigated in temperature range 80-320 K by steps of 20 K. The parameters such as barrier height, ideality factor and series resistance of this structure were calculated from the forward bias I-V characteristics as a function of sample temperature. It was seen that the ideality factor and series resistance were decreased; the barrier height were increased with increasing temperature. The experimental values of barrier height and ideality factor for this device were calculated as 0.808 eV and 1.519 at 320 K; 0.220 eV and 4.961 at 80 K, respectively. These abnormal behaviors can be explained by the barrier inhomogeneities at the metal-semiconductor (M-S) interface.

Saǧlam, M.; Ateş, A.; Güzeldir, B.; Yildirim, M.A.; Astam, A.

The CdS thin film has been directly formed on n-type Si substrate to form an interfacial layer between cadmium (Cd) and n-type Si with Successive Ionic Layer Adsorption and Reaction (SILAR) method. An Au-Sb electrode has been used as an ohmic contact. The Cd/CdS/n-Si/Au-Sb structure has demonstrated clearly rectifying behaviour by the current-voltage (I-V) curves studied at room temperature. The characteristics parameters such as barrier height, ideality factor and series resistance of Cd/CdS/n-Si/Au-Sb structure have been calculated from the forward bias I-V and reverse bias C-2-V characteristics. The diode ideality factor and the barrier height have been calculated as n = 2.06 and Φb = 0.92 eV by applying a thermionic emission theory, respectively. The diode shows non-ideal I-V behaviour with an ideality factor greater than unity that can be ascribed to the interfacial layer, the interface states and the series resistance. At high current densities in the forward direction, the series resistance (Rs) effect has been observed. The values of Rs obtained from dV/d(lnI)-I and H(I)-I plots are near to each others (Rs = 182.24 Ω and Rs = 186.04 Ω, respectively). This case shows the consistency of the Cheung′s approach. In the same way, the barrier height calculated from C-2 -V characteristics varied from 0.698 to 0.743 eV. Furthermore, the density distribution of interface states (Nss) of the device has been obtained from the forward bias I-V characteristics. It has been seen that, the Nss has almost an exponential rise with bias from the mid gap toward the bottom of conduction band.