Can, Erol

The increasing complexity and integration density of modern mixed-signal and high-frequency systems demand reconfigurable, precise, and fault-tolerant signal-routing architectures. Conventional switching matrices based on multiplexers or crossbar networks suffer from crosstalk, leakage, limited scalability, and weak fault tolerance, making them unsuitable for emerging precision analog platforms. Addressing these limitations, this work introduces the Diode-Based Programmable Network Array (DiProNA), a novel hybrid switching architecture that differs fundamentally from existing structures by combining MOSFET-based programmability with unidirectional diode-assisted conduction paths to achieve intrinsic fault isolation, current sharing, and enhanced thermal robustness. A comprehensive analytical model—developed using Thevenin equivalents, nodal analysis, and explicit inclusion of diode and MOSFET parasitics—is presented and validated through extensive circuit-level simulations. Clear modeling assumptions (such as quasi-static device behavior and linearized small-signal parasitics) are stated to ensure transparency and reproducibility. Quantitative comparisons with traditional multiplexer and crossbar matrices demonstrate that DiProNA achieves higher voltage accuracy, lower effective resistance, and significantly reduced short-circuit current. Series ballast resistors effectively constrain fault currents and mitigate thermal stress, enabling reliable operation under open-circuit, short-circuit, and partial-failure scenarios. Multi-source configurations further enhance efficiency and distribute power-thermal load, while dynamic evaluations confirm microsecond-level response times with minimal overshoot, supporting high-speed instrumentation front-ends. Collectively, the results position DiProNA as a scalable, efficient, and fault-tolerant routing solution suitable for adaptive data converters, SoC subsystems, wireless front-ends, and biomedical instrumentation. This work establishes DiProNA as a robust and versatile platform advancing next-generation programmable mixed-signal systems.

Gokyildirim, Abdullah; Yesil, Abdullah; Babacan, Yunus

In this study, an electronic model of a memristive-based 4D autonomous chaotic system with a line equilibrium is proposed. A memristor offers many advantages because of its superior properties for improving different circuits, e.g., chaotic circuits and systems. In particular, its nonlinearity and nonvolatile behavior provide a unique opportunity to design chaotic circuits. Therefore, we designed a flux-controlled memristor-based 4D autonomous chaotic system having a line equilibrium. The fundamental dynamical properties of the system are demonstrated with regards to equilibrium, Jacobian matrices, Lyapunov exponents, and bifurcation behavior. A nonlinear controller based on the Lyapunov stability method was also designed to control the novel system. Furthermore, it is controlled by only one state controller. As was expected, both theoretical and simulation results of the 4D chaotic oscillator were in good agreement with the experimental results.

Babacan, Yunus; Kacar, Firat

This paper presents electronically controllable neuron circuit-neuristor- based logic OR and AND gates using the same circuit topology. Here, only four neuristors are used to obtain both OR and AND gates which have three inputs and one output. The proposed circuit is electronically controllable and can be used as an OR or AND gate by changing only one voltage source without changing any circuit topology. All simulation results are obtained as expected from the electronically controllable logic gates based on the neuristor which composed of memristor.

Babacan, Yunus

This paper presents a new four-quadrant analog multiplier based on a dynamic threshold MOS (DTMOS). The attractive features of this DTMOS transistor-based multiplier are its supply voltages and total power consumption, which were determined as ± 0.2 V and 18.4 nW, respectively. In addition, the study found no influences of the bulk effect of the transistors used in the proposed multiplier circuit. The layout of the four-quadrant analog multiplier occupied an active area of 44.6 µm × 21.93 µm and was drawn using Cadence Environment software, while the post-layout simulation results were performed using Cadence Environment with 0.18 µm TSMC CMOS technology parameters. All theoretical results and post-layout simulations confirmed the performance of the proposed circuit.