Compact and Cost-Efficient Dual-Buck NPC Inverter with Dead-Time Elimination and Shoot-Through Suppression

Dead-time insertion is the conventional method for preventing shoot-through faults in neutral-point-clamped inverters (NPCIs), but it inevitably degrades output-voltage quality, lowers efficiency, and increases control complexity due to dead-time compensation. This article presents a novel transformer-based dual-buck NPCI (T-DB-NPCI) cell that inherently solves this problem at the topology level. The proposed structure not only eliminates the need for dead-time during normal switching transitions but also provides robust hardware suppression of destructive, long-duration shoot-through faults. The proposed cell is designed to safely withstand forced shoot-through faults of up to 2 μs, ensuring high reliability without requiring complex detection algorithms. The topology features a remarkably compact structure comprising only a single high-frequency transformer and one auxiliary diode, enabling all semiconductor devices to operate at only half the DC-link voltage. Furthermore, the streamlined structure allows for the use of standard sinusoidal pulse width modulation (SPWM), significantly reducing control complexity. Comprehensive results from a 425-W prototype achieving 97.4% peak experimental efficiency confirm excellent performance. A comparative analysis reveals an 8% improvement in power density (683 W/kg) and a 6% cost advantage over its closest counterpart. The T-DB-NPCI topology emerges as a highly promising solution where reliability and simplicity are critical. © 1982-2012 IEEE.